1. Field of the Invention
The present invention relates to semiconductor packaging technology generally and, more specifically, to a process for forming metal pillars and a solder layers on semiconductor devices for flip-chip bonding to a substrate.
2. Description of the Related Art
Copper pillars are a widely used technique for electrically interconnecting a flip-chip semiconductor device or “chip” to conductors on an organic-based substrate, such as a thin (less than one millimeter thick) glass-epoxy board, because copper pillar interconnects have superior geometric control, higher density, and electrical performance relative to solder bump interconnects. The copper pillars on the device's die pads, formed by selectively plating copper onto the die pads, connect to the substrate's substrate pads by using a solder layer between each pillar and the respective substrate pad to join the copper pillars to the substrate pads. Plating is usually used to form the solder layer onto the ends of the copper pillars.
To bond a flip-chip device to a substrate, the device and substrate are brought together and heated until the solder on the ends of the copper pillars melts and wets the substrate pads on the substrate, each pillar and solder combination forming a “joint”. Then the device-substrate combination is cooled down and the solder solidifies to bond the device to the substrate, forming a bonded device-substrate structure or “package”.
In order to insure all substrate-to-die joints are formed during bonding, all of the copper pillars and solder layers on the die before heating are to have the same nominal height. In addition it is generally desirable for all of the joints to have substantially the same diameter. However, having joints with the same diameter might not be desirable in all instances. For example, for carrying a large number of high-speed signals between the chip and the substrate, it might be desirable to use thinner than “normal” diameter joints spaced to provide a high density of signal paths while at the same time providing a desired transmission line characteristic impedance between the joints, e.g., 50 or 100Ω. In other instances where a large current is to be carried by a joint, e.g., a power supply connection, electromigration might with time cause failure of a joint with a normal diameter. To address the high current problem, multiple joints with a normal diameter are placed in parallel or one or more of the joints are formed with a larger or wider diameter than a “normal” joint so that the current density in each joint is less than a maximum amount that would otherwise cause the joint to fail from electromigration. However, using a conventional plating process to make joints with different diameters with substantially uniform height has been problematic. For a given electrochemical plating process and plating bath solution, the mass or volume per unit of time of the plated material is essentially a constant except for any local variations in the bath current density or concentration of all of the plating species in a particular plating bath. As a result, using a conventional electroplating process to form different diameter joints will result in a device with smaller diameter joints that are taller than adjacent larger diameter joints. The uneven joint height might not allow the shorter joints on the device to be completely attached, if at all, to their respective substrate pads, while all of the taller joints will be completely attached, thus causing the completed package to be inoperable or prone to high rates of failure in the field. Further, any warpage of the substrate might exacerbate this situation, possibly increasing the number of partial or incomplete joints.